Theatre

Beat the Supply Chain by Making your Own Chips!

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29:55

EOC 2024

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Matt Venn

Matthew Venn is a science & technology communicator and electronic engineer. He brings 20 years of engineering experience to create excellent and innovative learning experiences for people all over the world.

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FPGA Hardware Tools Open Source

Theatre

Beat the Supply Chain by Making your Own Chips!

Matt Venn

29:55 EOC 2024

Matt Venn

29:55

Over the last few years there has been a lot of movement in the world of open source silicon and we now have lots of options to design chips and even a few to get them manufactured. Ok While it's unlikely you'll be beating the supply chain anytime soon, in this talk I'll show you how to get started with simple chip design using free and open source tools.

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What was the main practical reason Matt Venn created Tiny Tape-Out (splitting a chip into many tiles) for hobbyists and students?

A To increase the manufacturing speed by running many small designs in parallel on different foundries.

B To guarantee participants receive manufactured silicon affordably by sharing the cost of one chip among many people.

C To make each participant's design proprietary while still using an otherwise open multi-project wafer.

D To reduce the number of transistors required per design so designs would fit in smaller process nodes.

E To bypass foundry qualification processes and avoid PDK requirements for each design.

Which end-to-end digital open-source ASIC flow did Matt identify as the most popular and commonly used for turning HDL into GDS?

A Yosys (as a complete end-to-end flow)

B Magic (as the primary digital ASIC flow)

C OpenLane (dependent on OpenROAD)

D ngspice (used for digital placement and routing)

E gdsfactory (as the standard synthesis-to-GDS flow)

According to the talk, what is a key current limitation of open-source toolchains when designing RF or high-frequency analog circuits?

A There are no PDKs available for mixed-signal processes like 130 nm.

B Open-source flows completely lack transistor-level SPICE models.

C They cannot perform inductance extraction from layouts, which is important for radio designs.

D Open-source tools cannot generate GDS files suitable for foundries.

E Digital synthesis tools in the open-source flow cannot optimize for timing.

What workflow did Matt suggest as the easiest no-install way for beginners to create a chip design and produce GDS for Tiny Tape-Out?

A Use the Wokwi browser-based editor and the Tiny Tape-Out GitHub Actions to build and produce GDS without installing local EDA tools.

B Manually draw masks on transparencies at home and mail them to the foundry to avoid software installs.

C Insist on using only proprietary closed-source EDA suites because they never require local installs.

D Buy an expensive $10,000 private shuttle run so you don't need to use open-source tools.

E Only work with FPGAs, since ASIC flows always require complex local installations.

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Upvotes Newest Oldest

Scott_H

Score: 1 | 2 years ago | 1 reply

Thanks, that was amazingly accessible to a non-EE. I had heard of tiny tape out, but assumed it would be far more complicated to design in silicon. Really liked the tools used to demonstrate concepts.

MattSpeaker

Score: 0 | 2 years ago | no reply

Thanks!

cijart

Score: 0 | 2 years ago | 1 reply

Thanks for sheding light to custom chip design with open source desing tools, and thanks for shairng your journey, and some experiences! Problem w/ custom chip design is that is strongly connected with manufacturing costs and foundry EUV technlogies.
India (in collaboration with Kunal Gosh's VLSI Design Ltd) has addopted this approach in therir university system, in a hope to democratize access to chip design tools and to achieve tape out of their own RISCV processors desgns.

MattSpeaker

Score: 0 | 2 years ago | no reply

Thanks!

IGate

Score: 1 | 2 years ago | 1 reply

Thanks a lot, great presentation!!!

MattSpeaker

Score: 0 | 2 years ago | no reply

thanks!

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