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Fixed-Point Filters – Modelling and Verification Using Python
Dan Boschen - Watch Now - Duration: 02:21:36
NEW: All files related to this workshop have been zipped and can be downloaded by clicking on the link in the left column "Click Here to Download Slides (PDF)"
Digital filters are commonly used in the processing of signals, whether they be wireless waveforms, captured sounds, and biomedical signals such as ECG; typically for the purpose of passing certain frequencies and suppressing others. Fixed-point implementation is attractive for lowest power lowest cost solutions when it is critical to make the most out of limited computing resources, however there can be significant performance challenges when implementing filters in fixed-point binary arithmetic. When a fixed-point implementation is required, a typical design process is to start with a floating-point design that has been validated to meet all performance requirements, and then simulate a fixed-point implementation of that design while modifying the precision used to ensure the requirements are met.
In this workshop, Dan takes you through the practical process of simulating a fixed-point digital filter using open-source Python libraries. This is of interest to participants wanting to see a motivating example for learning Python as well as those with experience using Python. Also included: a quick recap of basic filter structures and filter performance concerns. A significant background in Digital Signal Processing (DSP) or digital filter design is not required. Having taken an undergraduate Signals and Systems course is sufficient. For a more detailed review of binary fixed-point operations and notations that will be used in this workshop, please attend Dan's Theatre Talk "Fixed-Point Made Easy: A Guide for Newcomers and Seasoned Engineers" that will be scheduled before this. After attending this talk, the participants will be equipped to confidently convert a given filter implementation to fixed-point prior to detailed implementation. If you have a floating-point filter design and need to implement it in fixed-point, this workshop is for you!
Hi Mathieu, thanks for these insightful comments.
The final bit sizes shown are not necessarily the optimum bit sizes, and optimum would depend on a total allowable SNR degradation as well as allowable reduction of the stop band rejection. What I do is simply iterate on the bit widths while monitoring the performance of both (SNR degradation as well as achieved stop band rejection) with a maximum allowable degradation in mind. As mentioned in the talk, I used a sine wave as it would be easiest for a wider audience to follow the quick demonstration but recommend actually doing this with a test signal that contains the reference waveform that fills the bandwidth used as well having elevated noise at worst case interference levels (and the reference waveform is used throughout to confirm waveform quality with the EVM function). As far as setting the bit width between stages, a rule of thumb is that it should be higher precision than the final output (similar to the rule of thumb and for the same reasons that I demonstrate that the multiplier outputs in an FIR filter should be higher precision than the final output of an FIR filter) but how much really depends on the gain (and structure!) of the subsequent stages- so by doing the iterative approach I use with Q(m,n) format, we are adjusting both gain and precision in between each stage and with that quickly seeing each stages contribution to the final output performance. Not demonstrated, but I recommend further using the floating point model to create a reference waveform at each major node (in between the SOS sections), and then with that the SNR degradation can be monitored directly at that stage. Ultimately you work with an SNR budget representing the total allowable degradation for the whole filter, and balance how much of the budget to use for each section. You'll see in this the sensitivity of the stages such that the distribution of the noise degradation is optimized based on bit width growth (growing the bit width of one shrinks that of another and we find the optimum balance with that in mind). I am developing a tool that automates much of this while also displaying conveniently the total resources (adds, delays, mults) used - but in this talk I didn't want that educational detail of manually tuning the filter hidden.
I am happy you noticed the utility (and sophistication) of my EVM function. I call this a "Rho Tool" which is equivalent to what we may traditionally call EVM when limited to decision samples only. However here for a sine wave, or any other reference waveform when we are concerned with the accuracy of every sample provided, the "Error Vector" is the difference between the sample and its noise free replica at every sample. I detail the process of creating such a tool here: https://dsp.stackexchange.com/questions/86682/issue-with-snr-and-sinad-measurement-using-matlab-functions-in-specific-cases/87596#87596 . I have implemented this for very high dynamic range, high accuracy measurements and the 2D search you mention was accomplished very efficiently via binary search (log2(N) steps to converge to floor).
All files have been zipped and can now be downloaded from the "Click Here to Download Slides (PDF)" link on the left.
Thank you, Stephane. And thank you, Dan, for a very well-done and highly interesting session. Bravo.
One of my motivations for attending the EOC is to learn from experts like Dan. The value of learning from such experts is incredible. In Dan's case, I learn something new every time I see his presentations. His methods, and resources are well beyond what many courses I've attended in person. Dan's attention to detail is obvious as is his passion. I plan to retake a few of his courses, but I would like to see what he offers for the material he said he is putting together in this presentation for a possible filters course. I find Dan's courses well worth the cost and time attending.
Thank you for the kind words David. It’s always great to have such interested co-learners such as yourself!
Cannot join -- "the host has another meeting in progress"
This live event is over. A recording will be posted later today.
Ah, my mistake. I thought the schedule said 10am.
Yes, 10 am EDT.
11:04:52 From Thomas Schaertel : Will the notebook be available to the attendees? 11:10:43 From Dave Comer : floating point 11:11:05 From Michael Kirkhart : fixed point 11:11:18 From Keith J : I would think fixed point 11:11:19 From BobF : Reacted to "fixed point" with 👍 11:17:45 From Keith J : 👍 11:19:01 From Ross K. : I'm confused about the noise floor. Why is there a qap between the predicted value and the value shown on the plot (previous slide)? 11:20:22 From Puru Patil : SNR = Number Of Bits * 6 dB/bit + 1.8dB 11:21:00 From Ross K. : Yes 11:21:23 From BobF : Theory meets Practice ! 11:21:36 From david.pavlovic : Does that mean that if we use lower number of FFT samples, the noise floor would increase? 11:21:46 From Vishwa Perera : Does the harmonics in the second figure (16bits) affects somehow in the design process? 11:23:04 From robin : does this formula exclude the processing(correlative) gain you get from the FFT? 11:23:16 From Vishwa Perera : Reacted to "Does the harmonics i..." with 👍 11:23:46 From Gonzalo : to get to this conclusions, I guess we should do a coherent sampling of the periodic signal, otherwise the noise won't be that white and distributed, am I right? 11:23:47 From robin : thanks! 11:25:50 From BobF : What are the significant effects of different ADC converter design structures? 11:34:04 From BobF : Any particular modulation ? 11:39:47 From Dave Comer : Reference: Widrow, “Quantization Noise”, ISBN 780251886710 11:40:34 From BobF : Reacted to "Reference: Widrow, ..." with 👍 11:41:36 From mnapier : Google doesn't find that ISBN 11:42:47 From mnapier : I see it now. 11:43:57 From Dave Comer : My book had a sticker coving the ISBN, so that is proably why.. I see if I can find the reference on Amazon and wil post it in the comment for the talk. 11:44:28 From mnapier : https://www.amazon.com/Quantization-Noise-Computation-Processing-Communications/dp/0521886716 11:46:33 From mnapier : https://isl.stanford.edu/~widrow/papers/j1996statisticaltheory.pdf 11:47:05 From Dave Comer : Thanks mnapier 11:49:41 From BobF : Effects of non-linearities? 11:54:37 From BobF : Friis Formula ! 12:00:26 From Michael Kirkhart : If not careful, you can make an IIR filter an IIR oscillator! 12:03:49 From BobF : Reacted to "If not careful, yo..." with 😮 12:04:14 From Agustin : m and n are in ARM format? 12:05:49 From BobF : Sweet ! 12:10:40 From Puru Patil : so this is for simulation and trying out different configurations of m and n combination and the math involved right? what are the suggested fp libraries to replicate the final model on the target e.g. CortexM4 or smaller MCUs? 12:12:13 From Puru Patil : ok great thanks..looking forward 12:12:19 From BobF : FPGA relevant ! 12:18:55 From BobF : Constraints when adopting microPython ? 12:19:01 From mnapier : Truncation doesn't work well in feedback loops. The 1/2 bit error keeps accumulating. One cute way to avoid the round is to append a "1" to the end of the bits. 12:22:15 From Agustin : Could you maximize the window? 12:22:21 From Agustin : Thanks 12:22:33 From Joaquin Castellanos : ok 12:22:34 From Agustin : Good 12:25:29 From BobF : Slightly off topic but any particular modulation scheme that's a personal favourite? 12:26:21 From Puru Patil : and particular fft style/type your fav? 12:26:55 From Puru Patil : cooley/tuckey etc 12:26:57 From Puru Patil : yes 12:27:06 From Puru Patil : ok 12:27:23 From mnapier : Winograd FFT, relative prime stages. Very low numeric noise. 12:29:42 From Keith J : Loving the presentation - definitely for those who need to live and breathe filters. So just a user who likes the product, but for people who aren't filter experts but users of filters, you may want to check out ASN Filter Designer. It's a subscription product but lets you design and simulate filters and then output source code. For ARM users, also uses the special instructions built into the system... https://www.advsolned.com/asn_filter_designer_digital_filter_software/ 12:31:08 From Puru Patil : 👍🏼 12:31:42 From BobF : A curse for many ... non-linearities ! 12:32:53 From Puru Patil : biquad 12:33:17 From BobF : Reacted to "biquad" with 👍 12:41:45 From BobF : dB referenced to carrier? 12:47:29 From Brandon Michelsen : Is there a separate link for the PDF of this notebook? It looks like the PDF on the EOC website is just the presentation slides. 12:47:58 From Shilpa Anbalgan : Reacted to "Is there a separate ..." with 👆 12:49:01 From Vishwa Perera : Reacted to "Is there a separate ..." with 👍 12:49:05 From Puru Patil : any guidance on how to decide what bits to choose for processing e.g. for12bit ADC on 32-bit MCU e.g. cortex M4 target OR it's based on whatever simulation experiment we find to expectation? 12:49:07 From Vishwa Perera : Reacted to "Is there a separate ..." with 👆 12:50:30 From Puru Patil : you should have DSP for medical applications course too. It can be highly valuable12:50:57 From Puru Patil : I wish you were instructor for DSP during my MS program :-) 12:51:05 From Shilpa Anbalgan : Reacted to "I wish you were inst..." with 👍 12:51:34 From BobF : Applications - Anything where an ADC is present, ultimately. 12:52:17 From Puru Patil : Applications - Anything where an ADC is present, ultimately. 👍🏼 12:59:44 From Joaquin Castellanos : Any chance to have this course in 4 week / 5 week format ? (including the other presentation, available tools, different examples and short discussion about related wireless fundamentals) 13:00:33 From Joaquin Castellanos : Thanks 13:06:23 From BobF : I remember doing sensitivity analysis in analogue filter design (component level). Is there a similar analysis in the digital domain (at the digital component level)? 13:13:07 From BobF : The digital components themselves, ADC structures etc 13:13:44 From BobF : P-Z - why not ;<) 13:14:01 From Gonzalo : so what is the big ‘why’ do we still use fix point filters today? One answer I could guess is less cells used in an FPGA implementation, but today floating point in MCU seems ubiquitous. 13:14:40 From mnapier : Would you post an example of an FIR noise analysis? 13:16:37 From Keith J : Thank you! 13:16:41 From Aaron Olowin : Great workshop! Thanks a lot. 13:16:45 From René Andrés Ayoroa : Thank you Dan 13:16:45 From Joaquin Castellanos : Thanks 13:16:47 From Michael Kirkhart : This is really good stuff! 13:16:58 From Jason Sachs : thanks!!! 13:16:59 From mnapier : Thank you much. 13:17:00 From Gonzalo : Thank you very much, it was very interesting for me 13:17:00 From Charles Miller : Superb session. Thanks, Dan. 13:17:05 From Vishwa Perera : well put presentation and content. 13:17:09 From BobF : Great fun 13:17:09 From Vishwa Perera : Thank you 13:17:16 From Agustin : Thanks Dan! really good presentation. 13:18:00 From Puru Patil : Amazing workshop - thanks DAn, Stephane!
Hi, thanks a lot for this excellent presentation from a subject that way underrated today, I got a lot of value from it.
I just have few questions :
1) I did not get why the SOS#1 and SOS#2 output formats were set to 20 bits width (maybe I missed the reason in the presentation).
Did you resized the SOS#1 and SOS#2 output formats to smaller size in order to "relax" constraint on the downstream coefficients ?
Is there a rule of thumb to select the datapath width between second-order-sections ?
Should not we try to limit the quantization noise as much as possible in the first section of the filter, so that less noise is cascaded through the chain ?
2) Finally, as an exercise, I would like to run the jupyter notebook, therefore I want to replicate the EVM function
I never really computed EVM for sinewaves.
Do have to perform a 2D search to find the best {delay, magnitude} of the output vs the reference
and then compute the error vector ?
I don't need the code, just let me know If I am on the right way ;-)
Best regards