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RISC-V CFU: The Nexus of Embedded Software and FPGAs
Mohammed Billoo - Watch Now - EOC 2025 - Duration: 32:08
RISC-V’s instruction set architecture (ISA) has enabled seasoned embedded software engineers to experiment with FPGAs since numerous open-source RISC-V cores can be flashed onto an FPGA. One of the exciting features of the RISC-V ISA is the Custom Function Unit (CFU), which enables a framework to support custom operations in hardware that is accessible from software. In this talk, Mohammed will demonstrate the process of interacting with a RISC-V CFU using embedded software.
Excellent presentation!
This was different from most other presentations - and very interesting. I enjoyed how you show the obstacles that will cost a lot of time to fix, and then normally are quickly forgotten. These things are important if one should venture into this.
I understand that you may be able to create "cheap" IP for your own MCU, but will this be blocked by similar higher prices on FPGAs if you want to actually market a product?
Also - will you upload your slides?
BR Klaus Elk
Mohammed,
your presentation was a highlight for me, because I'm also trying to refresh my knowledge on FPGA. Long time ago, there were PLD (programmable logic devices), those getting more and more feature rich (so to speak) and culminating in ASICs and then FPGAs. At times I used the Lattice Diamond software, before I finally found the FPSlic from Atmel, which combined a real CPU and a FPGA. But my adventures ended when the costs for the tools rose, so you have to stick with the manufacturer. While the VHDL/Verilog was portable, the rest was not, nor the tools you are familiar with. I sometime buy a board like you did, I try to program those FPGAs, but with open source tools it is somewhat really difficult. I very interested, how your project with RISC-V evolves. This is not a traditional ISA, as it has no branch and compare instructions as you are accustomed with other controllers, though it's really fast! But to fix energy consumption (how to implement hibernate or sleep) is another issue.
Thanks a lot for sharing your adventures!
Thomas
Hi Thomas,
I'm glad you found value in my talk. I presented a talk similar to this at FOSDEM this year, hoping to get feedback/help from "real" FPGA engineers. One of the suggestions was to try LatticeSemi's Radiant tool with my design, targeting the FPGA on the OrangeCrab. If the design works as expected with the vendor tools and doesn't work with the open source tools, then I was instructed to create an issue with the open source project (the person making the suggestion was adamant that the open source tools should generate functional outputs). I guess that's the advantage of open source tools. With vendor-specific tools, you have to pay for support and hope the vendor takes you seriously.
I've also learned that it's rare in the FPGA world to dive right into hardware. You always simulate first! This is a fascinating journey I'm looking to continue, to hopefully become a "real" FPGA engineer!
Fantastic presentation! As someone who works with FPGAs, I’ve been increasingly curious about RISC-V—especially with Altera’s Nios V softcores gaining traction. I'm always fascinated by CPU and MCU architectures and how they actually work at the hardware level. You brought up some really interesting points and will definetely take a look at NeoRV32! Personally, I find learning about retro game consoles and trying to emulate them on FPGAs a super fun and insightful way to dive deeper into both processor architecture and FPGA design.