Theatre

Compact Heterogenous Computing Platforms

Alexopoulos Ilias

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40:59

EOC 2022

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Alexopoulos Ilias

Mr Alexopoulos Ilias received his B.S. degree from the Automation department of T.E.I. of Piraeus in Athens Greece in 1996 and his MS degree from Brunel University in 1999; now he is a PhD candidate at University of Nicosia. With more than 20 years of experience in embedded system design, product development and involved in numerous projects he gained experience in multiple domains in sensing, DC motors, prototyping, control systems, DSP, FPGAs, RF, Certifications, testing and system engineering. He is also an inventor with patents in US and EU, and recognition of work within companies and the open-source community. Currently developing low-cost heterogeneous embedded platform that consists of a two-chip solution with 32-bit microcontrollers and a tightly coupled FPGAs, with the relevant ecosystem of firmware and hardware to support rapid application development.

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Topics Covered

FPGA Hardware Microcontroller Architecture

Theatre

Compact Heterogenous Computing Platforms

Alexopoulos Ilias

40:59 EOC 2022

Alexopoulos Ilias

40:59

It is difficult to create a common platform to support completely different applications. In this presentation we will examine heterogenous platforms that tightly couple microcontrollers with FPGAs to increase computing capacity, provide flexible interface capabilities or use other features. We will examine how to setup a link between Coldfire and Spartan 6 devices through mini-flex bus. Bus differences for Kinetis devices will be noted, that shows the advantages of these newer devices and some application examples will be shown.

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What did Alexopoulos identify as the primary practical advantage of tightly coupling a microcontroller with an FPGA over an external bus?

A Make the FPGA appear as a native peripheral to the microcontroller via an external bus, enabling hardware extensions and modularity.

B Completely replace the microcontroller so all control and datapath logic run inside the FPGA.

C Avoid any FPGA configuration step by using only flash-based FPGAs that never need reprogramming.

D Minimize PCB cost by using the FPGA to remove all external RAM and I/O driver circuits in every design.

E Guarantee deterministic real-time behavior by running the whole system under Linux on the FPGA.

Which key bus-interface feature did Alexopoulos highlight as a major advantage of Kinetis devices compared with ColdFire in tightly coupled MCU–FPGA systems?

A Kinetis adds a transfer-acknowledge (TA) signal and byte-lane control so peripherals can indicate readiness and support byte enables.

B ColdFire provides transfer-acknowledge and byte-lane by default, while Kinetis removed them to simplify timing.

C Kinetis replaces the external parallel bus entirely with an SPI-like serial interface, eliminating bus transactions.

D The only difference is that Kinetis runs at a different voltage level than ColdFire, with no protocol differences.

E Kinetis requires the FPGA to be the bus master at all times, whereas ColdFire always remains the slave.

Why must you implement clock-domain crossing logic when the microcontroller bus clock and the FPGA internal clock are different?

A Because the bus clock from the microcontroller may not be related to the FPGA's clock, you must add clock-domain crossing logic to safely transfer signals between domains.

B You can avoid clock-domain crossing simply by adding more bus wait states; that eliminates the need for any synchronization logic.

C Using the Address Latch Enable (ALE) signal to latch addresses automatically synchronizes clocks, so extra logic is not required.

D Clock-domain crossing is unnecessary when the FPGA is configured initially in GPIO mode—synchronization is only needed after switching to bus mode.

E If the FPGA runs at a higher frequency than the bus, timing issues disappear and no crossing logic is needed.

When creating a UVVM-based testbench for a mini-FlexBus-connected FPGA that contains both block RAM and SDRAM, why did the speaker recommend configuring wait-state behavior in the bus functional model?

A Because internal block RAMs are zero-wait-state but SDRAM can require many cycles (e.g., 10–15), the model must emulate those wait-states so tests reflect realistic timing.

B Because UVVM always assumes zero wait states and therefore cannot model SDRAM timing at all unless you switch to a different test framework.

C You only need to model wait states when using Kinetis devices; ColdFire-based setups never require wait-state modeling.

D Wait states are primarily relevant for block RAM since block RAM typically needs many cycles to respond, while SDRAM is always single-cycle.

E Including wait states in the testbench will physically slow down real hardware block RAM accesses, so you should avoid modeling them.

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