David Moore is the Director of Engineering at Micro Digital. He has focused the past few years on developing SecureSMX®, as well as managing the developers and codebase, working with customers and partners, and making ongoing contributions to product quality. For many years, he maintained and extended the SMX® RTOS kernel and middleware components. Initially focused on x86 product development, he implemented the ARM and ARM-M (Cortex-M) ports of SMX and supported many new processors. He holds a degree in Information and Computer Science from the University of California, Irvine and is a member of the Phi Beta Kappa honor society.
A typical embedded system has no security structure. If a hacker breaks in anywhere he has access everywhere — to the keys, critical data, and everything. Secure coding is a great thing to do, but it only takes a single flaw to compromise the whole system, and on a system with thousands of lines of code, it could take a long time to find and fix all problems. It’s a never ending battle because new exploits are conceived continually. Partitioning greatly limits the scope of an intrusion and allows focusing secure coding efforts on the most critical partitions. This talk focuses on use of the Cortex-M Memory Protection Unit to partition the application and RTOS for security. After introducing the MPU and partitioning briefly, it discusses novel techniques at a fairly detailed level. It shows the mechanics with code and build file snippets.
Thank you for your talk - I am programming ARM Cortex-M3 and Cortex-M4 and earlier I was skipping MPU part of the hardware in PDF chip documentation because it was relatively short.
Thanks for watching. The chip manuals usually don't cover the MPU because it is defined by ARM in their docs. You can find them easily with Google and download the PDFs:
v7: "arm 0403e" and see section B3.5 Protected Memory System Architecture, PMSAv7
v8: "arm 100699"
Even better is to get Joseph Yiu's book The Definitive Guide to the ARM Cortex-M3 and Cortex-M4. It's the reference standard for the Cortex-M processors.
Thank you for your talk - I am programming ARM Cortex-M3 and Cortex-M4 and earlier I was skipping MPU part of the hardware in PDF chip documentation because it was relatively short.