Home > On-Demand Archives > Talks >

Safety Critical System Design on ARM Cortex-M

Suraj Joseph - Watch Now - EOC 2024 - Duration: 43:35

Safety Critical System Design on ARM Cortex-M
Suraj Joseph

Learn how to build resilient, safety-critical embedded systems, and discuss practical techniques to implement:

  • Freedom from Interference (FFI) in mixed criticality systems
  • Program Flow Monitoring
  • Memory Partitioning and Task Isolation
  • Fault Management
  • Security

The talk will be structured as a case study of an automotive ECU used on a modern self-driving vehicle, utilizing FreeRTOS and an ARM Cortex CPU.

M↓ MARKDOWN HELP
italicssurround text with
*asterisks*
boldsurround text with
**two asterisks**
hyperlink
[hyperlink](https://example.com)
or just a bare URL
code
surround text with
`backticks`
strikethroughsurround text with
~~two tilde characters~~
quote
prefix with
>

DJC
Score: 0 | 1 month ago | no reply

Great talk!

SimonSmith
Score: 0 | 2 months ago | 1 reply

Great talk and Q&A! It ties in with Elicia’s well on hard fault handlers. There was a detailed talk on MPUs in a previous EOC by Jean Labrosse. I worked on an aerospace project once to DO178C Level A where they used qualified code generators from a model for the application (manual code for lower layers), which helped with the safety case.

SurajSpeaker
Score: 1 | 1 month ago | no reply

Thanks for the recommendations! A qualified code generator can definitely be a viable strategy, and help ensure program correctness.

OUR SPONSORS

OUR PARTNERS