Super-Simple Tasker - Hardware RTOS for ARM Cortex-M
Super-Simple Tasker (SST) is a preemptive, priority-based RTOS kernel fully compatible with Rate Monotonic Analysis/Scheduling (RMA/RMS). It was initially published in 2006.
This session will present a unique hardware implementation of a modern version of SST for ARM Cortex-M (M0, M0+, M3, M4, M7, etc.).
The session will begin with introducing preemptive but non-blocking multitasking with so-called basic tasks (as defined in the OSEK/VDX/AUTOSAR operating system). Such tasks are ideal for executing event-driven state machines (a.k.a. active objects), which are also non-blocking and handle events in a run-to-completion fashion.
Next, you will see how these basic tasks can be mapped to ARM Cortex-M interrupts and how to program the NVIC interrupt controller to manage both interrupts and basic tasks.
The bulk of the session will demonstrate various preemption scenarios, including inter-task communication and the compatibility of SST with RMA/RMS. The demos will utilize a logic analyzer and will run on a low-end ARM Cortex-M0 and on a high-end ARM Cortex-M7 with FPU.
If you are interested in real-time performance, you should see SST in action. SST is available on GitHub under the permissive MIT open-source license. SST is likely the most efficient and performant RMS-compatible RTOS kernel for ARM Cortex-M.