Why your FPGA Design Might Need a Softcore Processor – What are the Options ?

Adam Taylor - Watch Now - EOC 2022 - Duration: 41:29

Adam Taylor

Abstract Test Your Knowledge Questions & Comments

FPGA are great for implementing highly parallel structures for image, signal, data processing and algorithms. These structures are ideal for implementation in programmable logic however, the control, configuration, interfacing and man machine interfacing require more often than not sequential processing. Of course for simple applications Finite State Machines can be used however designing, modifying and maintain which makes the difficult to implement complex control structures. The solution is to implement a simple soft core processor in the FPGA, this session will explore what our processor choices are proprietary vs open source, the decision matrix for implementation and trade-offs which occur when we decide to include the softcore processor in the FPGA.

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According to the talk, what is the primary reason to replace a large, complex finite state machine (FSM) in an FPGA with a soft-core processor?

A Because soft-core processors always use fewer FPGA resources than FSMs.

B Because FSMs cannot implement sequential behavior at all in programmable logic.

C Because large FSMs become difficult to manage, verify, debug and maintain as they grow, and a soft-core makes complex sequential control easier to change and observe.

D Because a soft-core processor gives the same parallel throughput as dedicated logic for algorithms like image processing.

E Because soft-cores eliminate the need for any interconnects or peripherals.

What key trade-off does Adam Taylor highlight when choosing a soft-core processor implemented in FPGA fabric versus a hard-core processor on a SoC?

A Soft-core processors always outperform hard-core processors in raw CPU speed.

B Soft-core processors consume programmable-logic resources and limit ability to fully power down or reconfigure the fabric, while hard-cores give higher performance but come with board-level overheads.

C Hard-core processors cannot access programmable logic at all, so they are unsuitable for heterogeneous systems.

D Soft-core processors remove the need for any security measures like bitstream encryption.

E Soft-core processors require external DDR for all applications, so they are never suitable for simple control tasks.

For small MCU-like soft cores inside an FPGA, which boot/run memory approach does the speaker recommend as the simplest and why?

A Always run the application from external DDR because it is faster and simpler.

B Run the code from block RAM (BRAM) initialized by the FPGA bitstream to avoid external non-volatile memory and a complex bootloader flow.

C Store the executable only in QSPI flash and let the processor fetch instructions directly from flash without any BRAM involvement.

D Use eMMC as the primary runtime memory for small MCU cores to simplify the FPGA bitstream.

E Embed a full Linux filesystem in BRAM for small MCU cores to get better debugging tools.

Which AXI VALID/READY handshaking rule did the speaker warn is critical to avoid deadlock in AXI designs?

A READY must be asserted by the receiver before VALID is ever asserted by the transmitter.

B Once VALID is asserted by the initiator it must not be deasserted until READY is received; READY may be withheld until the receiver can accept data.

C The initiator should withhold VALID until READY is asserted to prevent back-pressure and ensure safe transfers.

D VALID and READY can be toggled freely during a transfer as long as address and data are stable at the sample edge.

E AXI handshaking is optional; using static waits in state machines prevents deadlocks more reliably.

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