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Amir Alavi

As an embedded software engineer and control systems researcher, I have designed different products in areas such as IoT, smart grid, industrial control systems, and communication networks. I employ the latest software and hardware development technologies, from real-time operating systems to embedded Linux. Model-based control system design and implementation is my main expertise. During my doctoral study at Queen Mary University of London, I have worked on the development of distributed multi-agent control systems that operate over wireless communications protocols. I am currently working on the design of control systems for quantum computers as an embedded software engineer at Riverlane.

Firmware Co-Design & Development for IP Cores in C++/SystemC using Verilator

Status: Available Now

Co-design of software and hardware for FGPA-based embedded systems has become a major challenge for tech companies, pushing them to follow development processes that require special care to lower the risks. The risk becomes a major factor for system on chip (SoC) solutions with integrated intellectual property (IP) cores that require custom firmware or driver development. A solution to this problem that has received a lot of interest in the last few years is by simulating the IPs and using them to design and validate the corresponding software stacks. Verilator is an open-source tool that is specifically developed for this purpose to simulate the IPs written in Verilog or SystemVerilog hardware description languages. In this talk, I am going to discuss the following topics for the audience:

  • A brief introduction to SystemC and simulation of logic blocks in C++
  • Common processes for co-design of firmware and FPGA IP cores
  • Introduction to Verilator and using it for creating simulation models from IP cores
  • Protecting IPs by encrypting their simulated models and sharing pre-releases
  • An example workflow for Verilog IP simulation and firmware design in C++
  • Analysis of simulation results with open source tools
  • Real-time simulation of verilated models with QEMU for system integration

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