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Firmware Co-Design & Development for IP Cores in C++/SystemC using Verilator
Amir Alavi - Watch Now - Duration: 52:31
Co-design of software and hardware for FGPA-based embedded systems has become a major challenge for tech companies, pushing them to follow development processes that require special care to lower the risks. The risk becomes a major factor for system on chip (SoC) solutions with integrated intellectual property (IP) cores that require custom firmware or driver development. A solution to this problem that has received a lot of interest in the last few years is by simulating the IPs and using them to design and validate the corresponding software stacks. Verilator is an open-source tool that is specifically developed for this purpose to simulate the IPs written in Verilog or SystemVerilog hardware description languages. In this talk, I am going to discuss the following topics for the audience:
- A brief introduction to SystemC and simulation of logic blocks in C++
- Common processes for co-design of firmware and FPGA IP cores
- Introduction to Verilator and using it for creating simulation models from IP cores
- Protecting IPs by encrypting their simulated models and sharing pre-releases
- An example workflow for Verilog IP simulation and firmware design in C++
- Analysis of simulation results with open source tools
- Real-time simulation of verilated models with QEMU for system integration
Hi Horaira,
Thanks a lot for your interest in my talk. Your understanding is correct as the software development might start after the hardware gets ready depending on the specific technology constraints (ex. access to emulators). However, you should separate the design phase from the development phase. In the design phase, which was the focus of my talk, you don't need the hardware to be ready. The software team needs to know enough information to start designing the software even before the hardware is designed in detail. Communication between HW and SW teams is the differentiating factor for co-design and classical design processes, but the difference is not limited to it only. Iterative functional decomposition is also a major improvement that co-design processes provide. I hope my answer was helpful, also if you have further questions/comments, please let me know. I would be very happy to get feedback from my audience.
Thanks, got the point :)
The gtkwave run at the end of the presentation was not visible. Otherwise, nice overview. Thanks!
Thanks a lot Eric for noticing and raising this issue. I will try to fix it.
A nice overview !
One question though, in slide Co-design Key concepts (at 6 minutes)
My understanding is in classic design generally SW will wait for HW , and HW SW mostly would be not running in parallel,
Based on image it seems only communication ib/w HW and SW is missing between these two approaches.