This was a highly interesting presentation reflecting ‘The World we live in!’. Thank you.
As prevention is always better than the cure, a couple of ideas.
Would an on-chip monitoring sub-system that could diagnose pin-loading anomalies be viable i.e. high pin counts, real-estate costs et al? Also, abnormal chip core functionality checks i.e. using AI techniques similar to what Darktrace has done at the application level but within the chip cores themselves?
For non-invasive (non-contact) attacks, especially electro-magnetic sensing but also potentially for light interference, would a monitored Faraday Cage at the silicon die level be manufacturable? This assumes that sufficient thought is given for normal operating thermal heat to escape, amongst other things!
Admittedly, your focus is teaching others SoC/FPGA security including how to perform such attacks i.e. highlighting potential security flaws as opposed to providing solutions to prevent them from occurring in the first place!
This was a highly interesting presentation reflecting ‘The World we live in!’. Thank you.
As prevention is always better than the cure, a couple of ideas.
Would an on-chip monitoring sub-system that could diagnose pin-loading anomalies be viable i.e. high pin counts, real-estate costs et al? Also, abnormal chip core functionality checks i.e. using AI techniques similar to what Darktrace has done at the application level but within the chip cores themselves?
For non-invasive (non-contact) attacks, especially electro-magnetic sensing but also potentially for light interference, would a monitored Faraday Cage at the silicon die level be manufacturable? This assumes that sufficient thought is given for normal operating thermal heat to escape, amongst other things!
Admittedly, your focus is teaching others SoC/FPGA security including how to perform such attacks i.e. highlighting potential security flaws as opposed to providing solutions to prevent them from occurring in the first place!