Workshop

Building Accelerated Applications with Vitis

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01:22:22

EOC 2021

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Adam Taylor

Adam Taylor is an expert in design and development of embedded systems and FPGA's for several end applications. Throughout his career, Adam has used FPGA's to implement a wide variety of solutions from RADAR to safety critical control systems (SIL4) and satellite systems. He also had interesting stops in image processing and cryptography along the way. Adam has held executive positions, leading large developments for several major multinational companies. For many years Adam held significant roles in the space industry he was a Design Authority at Astrium Satellites Payload processing group for 6 years and for three years he was the Chief Engineer of a Space Imaging company, being responsible for several game changing projects.

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Topics Covered

C FPGA Software Design

Workshop

Building Accelerated Applications with Vitis

Adam Taylor

01:22:22 EOC 2021

Adam Taylor

01:22:22

Do you want to benefit from the acceleration of programmable logic using C or C++, for your quantitative finance / signal or image processing or AI/ML applications. The Vitis Unified Software Platform enables developers to more easily tap into the benefits of Xilinx heterogeneous SoCs and accelerate their applications, without needing advanced hardware development knowledge. This workshop will provide an in-depth tutorial on how to get started with Vitis and Vitis AI.

Topics covered in this workshop include:

Vitis features and elements
Vitis libraries
OpenCL
Vitis development flows
Optimizing software for programmable logic implementation
Vitis AI for machine learning inference acceleration
…and more!

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Please log in or create an account to test your knowledge and see the answers.

Why does the speaker recommend using Xilinx accelerated libraries when moving algorithms from the processor into programmable logic?

A They remove the need to perform any HLS optimizations because the tools auto-optimize arbitrary C code into ideal hardware.

B They are pre-authored HLS-friendly implementations (domain-specific and common) that synthesize cleanly, avoid system calls, and are written for parallelization, so you don't have to rewrite library code.

C They are hardware IP blocks that you instantiate directly in Vivado without any software integration.

D They guarantee better performance than any hand-crafted HLS code in all cases.

E They are mandatory — Vitis will not accept user kernels unless they call these libraries.

What is the primary role of the Xilinx Runtime (XRT) in an accelerated Vitis flow?

A A hardware IP block placed in the programmable logic to accelerate AXI transfers.

B A set of APIs, libraries, and drivers that manage communication, memory, binary download, execution, and debugging between the host and the accelerator.

C A cloud-only service used on Alveo cards and not applicable to embedded Zynq/MPSoC targets.

D A replacement for the OpenCL programming model, requiring users to rewrite kernels in a new language.

E A GUI tool inside Vitis used only for visualizing waveforms and hardware connections.

Why should you use software emulation and hardware emulation before doing a full hardware build in Vitis?

A Because emulation produces the final bitstream faster than a full hardware build.

B Because emulation lets you quickly verify algorithms, find bugs, and explore HLS optimizations and pragmas without the long place-and-route turnaround of a full hardware build.

C Because emulation is required to generate the root filesystem and boot files for embedded targets.

D Because emulation automatically guarantees the same timing and performance as the final hardware implementation.

E Because emulation eliminates the need to ever run the hardware build step.

According to the talk, which description of OpenCL memory objects is correct?

A Buffer objects are device-only image structures; image objects are continuous blocks accessed via pointers.

B Pipes are random-access buffers used like arrays inside kernels.

C Buffer objects are continuous blocks of data accessed via pointers, image objects hold device-specific image data, and pipes are FIFO-style streaming data fed by the host.

D There are only two OpenCL memory object types relevant to FPGA: buffers and registers.

E OpenCL images are standard picture files stored on disk and automatically loaded by the runtime.

Which kernel-level optimization does Adam identify as increasing throughput by allowing new data to start processing each clock cycle, while not reducing overall latency?

A Completely unrolling loops to duplicate hardware and always reduce latency.

B Using native C doubles for accuracy so the HLS tool produces faster pipelines automatically.

C Pipelining, which lets you begin processing new data each cycle and increases throughput but does not reduce latency.

D Relying on a single small BRAM and serial accesses to simplify memory and improve throughput.

E Avoiding any pragmas and letting the compiler decide everything without guidance.

When creating a Vitis platform for an embedded accelerated application, which three elements must be combined to form the platform?

A A Vivado bitstream only, since software elements are added later on the board.

B Hardware configuration (processor system and PL interfaces), software elements (boot files, FSBL, U-Boot, XRT), and the Linux element (kernel image, root filesystem, sysroot).

C Only the DPU hardware description, the model zoo, and the quantizer settings.

D The OpenCL kernel sources, GCC toolchain, and a Windows driver package.

E A cloud account, an Alveo card, and a prebuilt container image.

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Upvotes Newest Oldest

EricS

Score: 0 | 5 years ago | no reply

Does Xilinx support developing OpenCL applications with Vitis using FreeRTOS instead of Linux?

RoccoBrandi

Score: 0 | 5 years ago | no reply

video stops at minutes 56:29, when launching hardware emulation. i have tried to reload the page several times but it always stops at the same point
EDIT: I can manually resume the video moving the time bar forward

AdamTaylorCEngFIETSpeaker

Score: 3 | 5 years ago | no reply

You can find all the slides and lab material here
https://github.com/ATaylorCEngFIET/EOC_Vitis

Stephane.Boucher

Score: 2 | 5 years ago | no reply

This workshop is made available pre-recorded and will be followed by a Live Q&A

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