Home > On-Demand Archives > Q&A Sessions >
Live Q&A - Back to the Future with Embedded Software (and Predictable Timing)
Henk Muller - XMOS - Watch Now - EOC 2021 - Duration: 24:08
Hi, a big bottleneck is memory access times. Thus, caches are traditionally used. How does XMOS deal with memory access time, is the internal 512kB RAM available to be read/written in 1 clock cycle?
Thank you for such an informative talk. When you say multiple (16 in this case) micros are used in a single chip, what about the power consumption and price increase for such an architecture. Also, as you mentioned caches were not used, I was little confused how memory synchronisation was taken care.
Hello Naveen, there are 16 logical cores, but these are implemented with just two physical actual cores. So pricing at volume is highly competitive. Each of the two physical cores has its own memory, and all eight logical cores in that physical core have single cycle access, so memory is effectively synchronised on a per-clock cycle basis.
Are interrupts still allowed with XCORE? It seems like there is no way around using interrupts to respond to external events. Thank you.
Thanks Henk for this intro. I've heard some good things about the "Transputer" from my "older" colleauges. I believe XMOS is a continuation of the Transputer? I am unfamiliar with the subject but it is facinating to learn that there is an alternative architecture to traditional micro-processor.
Are there trace techniques for bare metal functions/tasks?
How is interrupt tracing handled, and what is the overhead for this?