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Live Q&A - Back to the Future with Embedded Software (and Predictable Timing)

Henk Muller - XMOS - Watch Now - EOC 2021 - Duration: 24:08

Live Q&A with Henk Muller for the theatre talk titled Back to the Future with Embedded Software (and Predictable Timing)
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Score: 0 | 3 years ago | no reply

Are there trace techniques for bare metal functions/tasks?
How is interrupt tracing handled, and what is the overhead for this?

Score: -1 | 3 years ago | no reply

Hi, a big bottleneck is memory access times. Thus, caches are traditionally used. How does XMOS deal with memory access time, is the internal 512kB RAM available to be read/written in 1 clock cycle?

Score: 0 | 3 years ago | 1 reply

Thank you for such an informative talk. When you say multiple (16 in this case) micros are used in a single chip, what about the power consumption and price increase for such an architecture. Also, as you mentioned caches were not used, I was little confused how memory synchronisation was taken care.

Score: 0 | 3 years ago | no reply

Hello Naveen, there are 16 logical cores, but these are implemented with just two physical actual cores. So pricing at volume is highly competitive. Each of the two physical cores has its own memory, and all eight logical cores in that physical core have single cycle access, so memory is effectively synchronised on a per-clock cycle basis.

Score: 1 | 3 years ago | no reply

Are interrupts still allowed with XCORE? It seems like there is no way around using interrupts to respond to external events. Thank you.

Score: 0 | 3 years ago | no reply

Thanks Henk for this intro. I've heard some good things about the "Transputer" from my "older" colleauges. I believe XMOS is a continuation of the Transputer? I am unfamiliar with the subject but it is facinating to learn that there is an alternative architecture to traditional micro-processor.

12:03:36	 From  Stephane Boucher : https://www.embeddedonlineconference.com/theatre/Back_to_the_future_with_embedded_software
12:12:06	 From  Erwin : Does this mean that during Debug Session you need one core for Debugging?
12:13:56	 From  Erwin : Thanks
12:14:04	 From  Radu Pralea : So, essentially, this approach (architecture) aims at making concurrency + real-time very simple & straight forward, but only as long as you have less processes than number of cores (which is reasonable in so many practical scenarios), isn't it?
12:18:17	 From  Matt Liberty : How does XMOS stack up to other architectures with compute power per Watt?
12:18:58	 From  Erwin : Also DevKits are a little bit out of stock Right now!
12:19:25	 From  1 - Matthew Lai : Is the XMOS ISA similar to or quite different from RISC-V ISA?
12:21:26	 From  Matt Liberty : Yes.  Thank you!
12:22:54	 From  1 - Matthew Lai : Cool. Thanks.
12:23:03	 From  Radu Pralea : I remember such an approach back in the mid 2000s (I've even worked at a company that tried it): an array of simple but many cores: PicoChip. I've just googled, and XMOS and PicoChip seem to share some key people :) Could you comment, please? (also about the fact that after the acquisition (I think it ended with Intel acquiring Mindspeed) I've never heard of this architecture?
12:23:45	 From  Radu Pralea : indeed
12:24:23	 From  Radu Pralea : Thanks
12:24:23	 From  Keith J : Thank you Henk
12:24:31	 From  Ian Ross : Thanks, Henk!
12:24:36	 From  Steve Wheeler : Thank you.
12:24:51	 From  Carlos Amaya : Thank you
12:24:55	 From  RonCollinson : Cheers, Henk
12:25:03	 From  Erwin : Thanks a lot, interresting approach!