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What the FAQ is an FPGA
Clive "Max" Maxfield - Watch Now - EOC 2020 - Duration: 58:45
A lot of people design embedded systems. Some of them are the hardware design engineers who create the boards. Others are the software developers who program the boards. The one thing that most of them have in common (apart from mutual distrust of each other) is that they predominantly use microcontrollers (MCUs) as the primary processing element in their designs.
Most of them have heard of FPGAs, but all they typically know is that these devices can be programmed to perform different functions -- they don't know how. Similarly, most of them have heard about languages like Verilog and VHDL, but all they typically know is that FPGA designers use these languages to capture the design -- they don't know how these hardware description languages (HDLs) differ from programming languages like C/C++.
In this presentation, engineer, writer, and communicator Max The Magnificent (a legend in his own lunchtime) will rend the veils asunder and reveal all. Max says that we will be leaping from topic to topic with the agility of young mountain goats, so he urges attendees to dress appropriately.
Thank you very much for taking the time to comment -- I'm so glad you liked it -- which part did you find to be the most interesting and/or useful?
I would thank you very much for the presentation and the discussion.
Hi Kalilo -- that's very kind of you to say -- thanks so much -- I enjoyed myself (much like my dear old mom, the real trick is to get me to STOP talking LOL
Whenever I received an email that this presentation was popular, and later I saw more than 50 comments, definitely I had to see this!!! And I hope doesn't sound repetitive, but congrats for the great presentation! By the way, that was the first time I watched something about FPGA that really made me want to at least play with it :)
Important to note to anyone passing by this presentation, this Questions & Comments section is a valuable add-on to it, worth spending time here reading.
As my question, probably a silly one (or perhaps the hardest possible): one thing I never found out is how really FPGAs are made? Because mostly I've seen so far stops on "logic, reprogrammable blocks + I/O blocks", and for me the answer to my question seems something hidden inside multiple vaults of multi-billion companies, so something extremely proprietary... But, as we are having more "open-source" solutions getting to hardware (from Arduino to RISC-V, OpenPOWER), I'm hoping that there should be some discussion going on somewhere about "design your own FPGA chip".
On that, do you have any reference material on how FPGAs are made, or how to do your own FPGA? Even if it's some textbook example/lab exercise on a protoboard would be really helpful.
Thanks in advance.
Hi Cesar -- thanks for your kind words -- regarding how FPGAs are made -- I think you are asking about the architecture rather than the fabrication process. Each FPGA has its own architecture -- but they are based on logic cells each containing a look-up table (4-, 5-, 6, 7-, 8-input depending on the FPGA), register, multiplexer, etc. They also have additional stuff for things like carry-forward. Then various types of DSP and memory blocks -- then the interconnect. The higher-end FPGAs have some very sophisticated interconnect schemes.
I'm sure they regard a lot of this as being propitiatory, but if you read their data sheets you can get a lot of nitty-gritty details.
Excellent Presentation, Thanks for the talk, Very much impressed the explanation of the differences between Microcontrollers and FPGAs with pictorial depiction and pseudo code.
Hi Raghu -- thanks so much for the kind words :-)
Like always, great talk, Sir. Thank you.
I have been following you (not in the FBI style) for some time now, and you really are magnificent. Not only you explain complex things in a simple manner, but with the awesome diagrams, your explanations become even more fantastic. More power to you.
Thank you so much Mandeep -- you have no idea how nice it is to hear that someone appreciates the time and effort it takes to create those diagrams :-)
Out of curiosity, I came here to hear your great talk, Max! Thank you!
Awesome -- thanks so much Nazmul -- Happy Monday -- Max
Great talk. Thanks
Hi Sheshu -- thank you for taking the time to comment -- presenters always appreciate hearing that someone liked the talk :-)
Hi Max,
I just watched the video presentation and it's a great intro to FPGAs and the twist in logic needed to build code around them! And perhaps you won't get a chance to answer because the "live" part of the event ended. However, how much massaging needs to be done from a working FPGA design to an ASIC? It's the one step I haven't done yet ;-) Your talking about radiation reminded me of my days in Aerospace!
Hi Andrew -- oooh, that's a tricky one. Altera (now Intel) have a route to convert some of their FPGAs to ASICs/SOCs, but for most of the vendors it's a real pain -- the third party IP blocks are different, and the clocking schemes, and ... it just goes on. There was an startup FPGA company a couple of years ago that had a great solution, but they faded away (sad face). Actually, I think a relatively new company called Efinix may have a solution -- check out this column: https://www.digikey.com/en/articles/techzone/2020/mar/implement-edge-computing-using-efinix-quantum-enabled-fpgas
Hi Max! I will definitely check out that link! Thanks for the reply and presentation...like others here (and your other comments) I look forward to "What the FAQ Part II" ;-) (wink).
Hi Andrew -- did you see my "What the FAQ" columns on my Cool Beans Blog ( www.clivemaxfield.com/coolbeans )? I think you'll find some interesting ones there, from Celsius and Fahrenheit (I bet you'll learn something new) to AI and ML to the IoT to Augmented Reality. Also I have a couple of "What the FAQ" columns on EEJournal.com ( https://www.eejournal.com/?s=max+maxfield )
I'll definitely contact them! Maybe I'll try and write a paper/presentation for next conference as well. :-) [I still like the plain old ASCII emojis ;-) ] I checked out your coolbeans stuff after watching your video. In the past, I also worked with a dev team working Prognostic Health Management...so of course I have questions :-O. Health in this case was for an aircraft not a person. I'll send you an email :-)
Here's a few links for people getting started with AI/ML/CV (Computer Vision) that I think are pretty cool and you and others here might not know about. They can be run on a pc/laptop and are great [I think] for teaching/learning about AI/ML without having to get too heavy into the math.
A teachable, teachable AI ;-) Can also export the trained model for use in other applications. :-)
Teachable Machine by Google
Learning Computer Vision with Excel, YES Excel
Video Wake Words - MIT
The source code for the MIT demo is also available on github from the YT video.
I'll also connect with you on your other channels. Thanks again! Hope links help anyone just starting out with AI/ML/CV.
Awesome -- thanks so much for sharing this with the rest of us -- it would be great if you could give a talk at the next conference -- you can contact Jacob (the conference organizer) via his website at www.beningo.com
I believe Jacob and Stephane are planning on having an IoT Online Conference in the fall -- you should tell them (nay, demand!) they should invite me to present LOL
I came to refresh myself on FPGAs and because I've been a fan of Max's articles from EE TImes (and the Cool Beans Blog). I did not expect the discussion on ML and AI. I was surprised how few engineers had skills to implement these. I myself thought it was still in the realm of computer scientists. Thank you for introducing a pathway for embedded engineers to get their feet wet in ML and AI.
Hi Mjg -- you are very welcome -- I must admit that I thought AI and ML was out of my bailiwick until I ran across things like the TinyML book, NanoEdge AI Studio, and Hello FPGA. I'm planning on using these resources to build my own AI/ML system -- I'll be reporting back in future columns. I'm currently working on building a 12 x 12 array of ping pong balls each containing a NeoPixel (check out my Cool Beans column from yesterday www.clivemaxfield.com/coolbeans ) Happy Saturday!
Mr. Maxfield, your biting wit never fails to captivate me! Thanks so much for the luculent and stimulating talk! By the way, I think some of the viewers will be delighted to know you also maintain a Youtube channel (https://www.youtube.com/channel/UCQVqp_L4hKqF1uZ3tNo5MDw)
Also, I do hope someone in the Q&C can give a ballpark figure on how many FPGAs are sold annually.. (bet it's a honking big number!!) I too am interested to know =)
"...your biting wit never fails to captivate me..." That's me, 1/2 man, 1/2 beast, and 1/2 wit LOL Re the number of FPGAs sold annually, I would love to hear at least a ballpark. Re the number of FPGA designers in the world, this is something else I'd love to know. As I said in the talk, the best guess from one of the FPGA vendors was 100,000 to 200,000 -- the others basically shrugged and told me to tell them if I found out LOL My problem is that the numbers don't seem to add up. According to the IDC, there are about 1.2 million embedded software developers. My understanding is that there are about 5X more embedded S/W developers than H/W designers, so that would put the worldwide number of embedded H/W designers at 240,000. Out of all the hardware designers I know, I would have said that only 1 out of 20 knows FPGAs (and that's being generous) -- if this is true, it would mean that there are only around 12,000 FPGA designers in the world, but this seems low -- so what's wrong with my math?
1/2 man + 1/2 beast + 1/2 wit = 3/2 = 150%
So we should always aim at being 50% more than what we can be, oooohhh always dropping them furtive life lessons in cryptic tropes Mr. Maxfield!!!
240k vs. 12k both seem exiguous to the global average employed in tech., estimates sure are never easy to interpret hehe..
"1/2 man + 1/2 beast + 1/2 wit = 3/2 = 150%" -- I was brought up to excel LOL
What a great talk, thank you Clive. This is the first time I get to understand what's really the deal with FPGAs, very good explanations.
One thing I didn't get into is the concept that some devices support dynamic reconfiguration, where you can be reconfiguring part of the device while the rest carries on doing what it was doing. The implications here really make your brain wobble on its gimbals LOL
That´s amazing
It really is rather clever -- think of a pipeline where you have a function that reads data in, processes it, and then hands it over to the next function -- well, suppose that the processed data is stored in on-chip SRAM, and then you reconfigure the first function to be the second function, and that's where things start to get very interesting -- for example, an artificial intelligence (AI) you could be fine-tuning the FPGA hardware based on the type of data being processed. The mind boggles...
Mind boggles indeed! This is very inspiring and compelling. Just very recently I started fiddling with hardware (Micropython and the ESP32 board) but even when FPGA seem so sophisticated and with a tough learning curve I want to jump in. I checked the Hello FPGA board but it's not out yet. Could you recommend any other kits for starters? something that could work with opensource tool chains?
Most FPGA vendors keep their tool chains close to their metaphorical chests. The only open source FPGA tool chain that springs to mind is Project IceStorm http://www.clifford.at/icestorm/ along with the iCE40-HX8K breakout board http://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/iCE40HX8KBreakoutBoard.aspx
Hi Mr. Norberto and Mr. Maxfield!
Thanks so much for the links! This open source tool is half the price of Hello FPGA.
By the way, won't dynamic reconfig. risk the system going into an undefined state during operation? Or does it not implement the changes you make in real time?
Hi Justin -- this is the tricky bit -- the system has to be designed in such a way that any related processes pause until the reconfiguration has taken place. Consider a microprocessor -- only a fraction of the logic is used to execute each instruction -- similarly, in some cases, you might have 100 functions of which only 10 are in use at any one time -- in which case rather than use an FPGA that can contain them all (burning power while they aren't being used), why not use an FPGA 1/10 the size and only have the 10 functions loaded and running that are needed at any particular time?
Thank you Clive
I live to serve LOL
Hi Norberto -- that's wonderful news. I think when I lot of people first hear about FPGAs, they understand that these devices can be configured in different ways, but they don't realize all if the implications with regard to doing things in parallel. Take a simple DSP function like y = (a b) + (c d) + (e f) + (g h) where 'a' thru 'h' are all 16-bit integers, for example. Now assume you have to do this over and over again. In the case of an FPGA, you could instigate four 16-bit multipliers and an adder than can add the four results together, so -- by performing loop unrolling and pipelining of the C code -- you could perform all of the multiplications simultaneously in the FPGA (loop unrolling) while at the same time adding the results from the previous multiplication (pipelining).
You are right. I didn't know all that parallel power in FPGAs and it's quite impressive
Brilliant, and thanks for the info on John Horton Conway - I'm also a Scouser!
Hi Mike -- I'm so glad you liked the talk -- for any visitors originating out of the UK, a "Scouser" is defined as "a native or inhabitant of Liverpool, England," so the Beatles were also Scousers. Also, as a point of interest, this term derives from "Scouse," which is an accent and dialect of English originating in the northwest county of Merseyside.
Great talk!
Any recommendations for a good basic introductory book to programming FPGAs? I've been teaching VHDL with FPGAs and the book I was using (Yalamanchili) is out of print.
Thanks Erikm -- to be honest, I'm not sure what the best introductory book is at the moment (if an FPGA company is reading this, maybe they might think about contracting me to write one LOL)
Hello Max,
This is a very helpful Informative Talk, Hope to attend a Talk for you again.
I love the Part related to the Pipeline using the MUX (on 20:22) it is a very nice techniques, i know about the Fully/Partially parallel Techniques and a simple pipeline, but first time to know that pipeline can have some special techniques, where can i read more about this?.
Hi Mina -- I'm glad you enjoyed the talk -- I'm not sure if there's anything formal written about this technique, it's just something I think any FPGA designer would throw together if the occasion demanded it, but I'll ask around a few friends to see what they say.
Nice and informative session.
Hi Mrithyunjay -- thanks so much for taking the time to comment -- I really appreciate it :-)
Hi Max,
Great presentation, disappointed that you drew the Hello FPGA's while I was asleep.
I used OpenCL between ARM and DSP and this has worked well and it seemed logical to move to Arm and FPGA with OpenCL do you have any experience? and are there any pit falls?
Hi Andrew -- actually, you haven't missed the "raffle" for the Hello FPGAs -- I'd forgotten that people could keep on watching the presentation throughout the 2-day conference -- and even after that. In fact there are 3 people watching it as I type these words, and that's almost 24 hours after the original presentation. So now we're planning on giving it a few days to let more people see the presentation, and then we'll do the draw for the Hello FPGAs.
Thanks for presentation, I learnt a lot!
Hi Govid -- that's fantastic news :-)
Thank you for the presentation, very informative.
Thanks BrianT -- are you coming from a microcontroller background? If so, which parts of this presentation did you find to be the most "Ah, I see!" type thing?
Excellent presentation! Looking forward for future one!
Thank you Dskokic -- I'm happy you enjoyed it.
Hi Max,
Thanks a lot for your wonderful sharing.
Thank you for taking the time to comment -- I really hope this presentation proved to be useful, along with the additional resources I list at the end :-)
With regard to metastability, one of the points I was planning on making (but forgot in the excitement of the moment) was that when we use a microcontroller to read the state of one of its digital inputs, we don't worry about metastability -- in fact, I would go so far to say that most of the microcontroller-based designers haven't even heard about it -- the thing is that the people who design the microcontrollers themselves have already taken care of this for us -- but we don't have that luxury when working with FPGAs
Thank you Max. That was very interesting presentation. It is very good starting point into FPGA
Hi Andrew -- thanks for saying so -- did you also like the additional material on things like Radiation and Switch Bounce and Metastability?
Hi Max the switch bounce and metastability has been very useful - 20ms rule :). I have also really appreciated extra info about TinyML.
Can you please elaborate a bit more on certifying an MCU Vs FPGA for an aerospace industry safety critical domain, especially the cost aspect.
Oooh -- that's an interesting question. Actually, in this case I would defer to my friend Adam Taylor who is also speaking at this conference -- you can reach out to him on LinkedIn ( https://www.linkedin.com/in/adam-taylor-ceng-fiet-8a991713/ ) -- or email me at max@clivemaxfield.com and I'll introduce you via email. Adam is an expert in safety-critical stuff regarding MCUs and FPGAs -- he's led engineering teams that have flown both types of components in space.
Thank max. RIP, John Conway. My personal hope: that the brainchildren of Lord Byron's daughter and Apple's namesake will meet soon! (Lovelace + Turing = [brave] new world)
Hi there -- I hadn't realized how much John had contributed to mathematics until I read his biography, "Genius at Play: The Curious Mind of John Horton Conway" by Siobhan Roberts -- as I wrote in my column "RIP Game of Life Creator" ( https://www.clivemaxfield.com/rip-game-of-life-creator/ ), this was the first time I'd heard of "surreal numbers" (they really are a thing). Also, I hadn't realized that they didn't use a computer to experiment with different rules for the Game of Life -- they did it by hand using pebbles on a Go board.
Great talk and slides
17 & 67 is the answer, what is the question?
Happy Wednesday too! ;-)
Would the answer be 1 ?
Enjoyed this. Super presentation!!
Why, thank you so much -- it really means a lot as a presenter to hear from folks who enjoyed one's talk :-)
Fantastic presentation, thank you very much!
This was the second talk today to remcomend that book - so I have it on its way. Looking forward to catching up with the ML-hype.
Thank you for your kind comments -- I read somewhere that by 2025 the majority (which means more than 50% LOL) of embedded systems will have some level of cognitive (thinking. reasoning) capability -- so it behooves us to stay on top of this technology (whilst also polishing our Aluminum Beanies https://zapatopi.net/afdb/
Now I'm thinking of all the other things I wish I'd said -- for example, the two (or more) stage synchronizer is also used to effect clock-domain crossings -- the idea is that you might have different portions of your FPGA design running with different clocks and/or clock speeds that are not synchronized to each other, so you have to ensure that data moving from one domain to another is free of metastability.
Is there any guarantee that the metastable state will be over before the next clock tick ? If so, how ?
Sadly not -- this is where things get a little tricky -- the "recovery" time is a statistical thing -- I'm not sure as to the exact values, but it might be something along the lines of "You have a 99.9% probability that the metastable condition will have ended by the recovery time. One solution is to add more levels to your synchronizer. I'm not an expert here -- my chum Adam Taylor (who is also presenting at this online conference) is a Prof of Embedded Engineering and he's written papers on this stuff.
I see, that makes sense. Thank you for the answer and pointers, very interesting talk !
Different Level of Design Abstraction slide was very helpful. Thank you Clive! Mind blown :-)
Wonderful -- I'm so pleased you are enjoying it :-)
Hello everyone -- Happy Wednesday :-)
this is good